pericom semiconductor corp. www.pericom.com page 1 of 1 8/7/2008 mpb080002b pci ? , pcie ? and pci express ? are registered trademarks of the pci sig ? ( www.pcisig.org ) | greenpacket? is a trademark of pericom semiconductor product: pcie ? packet switch - 5-port/5-lane part numbers: pi7c9x20505gp greenpacket tm family product description the pi7c9x20505gp is a 5-port, 5-lane, pci express ? packet switch specifically designed to meet the latest green low-power, lead (pb)-free system requirements, such as laptop, docking stati on, and other mobile or power sensitive platforms. the name of the family, greenpacket ? , refers to pericom proprietary power saving technology. the pi7c9x20505gp provides one upstream port supporting x1, and 4 downstream ports that support x1 operation. the pi7c9x20505gp pr ovides users the flexibility to expand or fanout from a wi de range of i/o bridge such as mch, ich, nvidia, and it is a suitable solution for hba, surveillance, combo card and other applications. industry specifications compliance pci express ? base specification, revision 1.1 pci express cem specification, revision 1.1 pci-to-pci ? bridge architecture specification, rev 1.2 advanced configuration power interface (acpi) specification pci standard hot-plug controller (shpc) and subsystem specification revision 1.0 features non-blocking full-wired switching capability at 16 gbps when all 4 lanes are enabled peer-to-peer switching between any 2 downstream ports reliability, availability and serviceability o supports data poisoning and end-to-end crc o advanced error reporting and logging o hot plug support o ieee 1149.6 jtag interface support link power management o supports l0, l0s, l1, l2, l2/l3 ready and l3 link power state o active state power management for l0s and l1 state o beacon or wake# support in l2 state device state power management o supports d0, d3 hot and d3 cold o 3.3v aux power support in d3 cold power state port arbitration: round robin (rr), weighted rr and time-based weighted rr extended virtual channel capability: o two virtual channels (vc) and eight traffic class (tc) support o non-enabled vc buffer assigned to enabled vcs for resource sharing o independent tc/vc mapping per each port o provides vc arbitration selections: strict priority, round robin (rr) and programmable weighted rr supports isochronous traffic o isochronous traffic class mapped to vc1 only o strict time based credit policing header/data queue at each vc of each port o four-entry non-posted request header and data (vc0 only) queue o four-entry posted request header queue o four-entry completion header queue o 512-byte posted write data buffer o 512-byte completed read data buffer supports up to 256-byte maximum payload size power dissipation: 0.75w typical in l0 normal mode industrial temperature range -40 o to 85 o package: 17x17mm, 256-pin pbga, w/1.0mm ball pitch - pb free and 100% green. enhanced features programmable driver current and de-emphasis level at each individual port 150ns typical latency for packet running through switch without blocking supports ?cut-through?(default) as well as ?store and forward? mode for switching packets supports up to 256-byte maximum payload size advanced power savings o empty downstream ports are set to idle o clock to corresponding circuit is turned off when any port enters l1 or aspm l1 application host cpu i/o bridge x1 pcie pcie end p oint pcie end p oint pcie end p oint x1 pcie pcie end p oint pi7c9x20505 gp
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